1. Field of the Invention
The present invention relates to a semiconductor integrated circuit using an insulated gate field-effect transistor (hereinafter referred to as “MOSFET”), and more particularly, to a hysteresis input circuit whose logic level is provided with a hysteresis characteristic to eliminate misoperation or instability due to noise when an input signal of an input circuit is changed from a high potential to a low potential or from a low potential to a high potential, capable of securing a large enough hysteresis width even when a supply voltage decreases.
2. Description of the Related Art
Conventionally, for an integrated circuit, a digital circuit in particular, a hysteresis input circuit is widely used with an input signal terminal provided with a difference in the logic level between a rise and fall of an input signal, that is, a hysteresis characteristic so as to eliminate misoperation or instability due to noise. However, with the introduction of finer integrated circuits and reduction of withstand voltages, lower supply voltages are used in recent years and it is becoming impossible to secure a sufficient hysteresis width.
This type of conventional circuit will be explained below.
A general input circuit provided with a conventional MOS integrated circuit having hysteresis constitutes a circuit equivalent to an inverter circuit and adopts a circuit structure providing two types of ratio between a P-type MOSFET conductance constant βP and an N-type MOSFET conductance constant βN which are always dominated by an input signal and which are large factors determining the logic level and changing this ratio between the two types βP and βN according to a preceding state.
FIG. 7 shows a first conventional circuit example and has a first logic level determined by P-type MOSFETs 601, 603 and an N-type MOSFET 602 and a second logic level determined by N-type MOSFETs 602, 604 and the P-type MOSFET 601. An inverter circuit 607, P-type MOSFET 605 and N-type MOSFET 606 switch between the aforementioned first logic level and second logic level according to a preceding state and create a hysteresis characteristic.
Furthermore, FIG. 8 shows a second conventional circuit example and is described in JP58-182914A.
The second conventional circuit shown in FIG. 8 has a first logic level determined by P-type MOSFETs 701, 703, 705 and N-type MOSFETs 702, 704 and a second logic level determined by N-type MOSFETs 702, 704, 706 and P-type MOSFETs 701, 703. Then, an inverter circuit 707, P-type MOSFET 705 and N-type MOSFET 706 switch between the aforementioned first logic level and second logic level according to a preceding state and create a hysteresis characteristic.
Furthermore, FIG. 9 shows a third conventional circuit example and is described in JP10-154924A.
The third conventional circuit shown in FIG. 9 has a first logic level determined by P-type MOSFETs 801, 803, 805 and N-type MOSFETs 802, 804 and a second logic level determined by N-type MOSFETs 802, 804, 806 and P-type MOSFETs 801, 803. Then, an inverter circuit 807, P-type MOSFET 805, N-type MOSFET 806 switch between the aforementioned first logic level and second logic level according to a preceding state and create a hysteresis characteristic.
Furthermore, FIG. 10 shows a fourth conventional circuit example and is described in JP11-27114A.
The fourth conventional circuit shown in FIG. 10 has a first logic level determined by P-type MOSFETs 911, 915 and N-type MOSFET 912 and a second logic level determined by N-type MOSFETs 914, 916 and P-type MOSFET 913. Then, a latch circuit 924 made up of NAND circuits 917, 918 and an inverter circuit 919, P-type MOSFET 915 and N-type MOSFET 916 switch between the aforementioned first logic level and second logic level according to a preceding state and create a hysteresis characteristic.
However, the above described conventional hysteresis input circuits have the following problems.
First, in the conventional circuits shown in FIG. 7, FIG. 8, and FIG. 9, an equivalent circuit in forming the first and second logic levels can be reduced to the inverter circuit constructed of a P-type MOSFET and N-type MOSFET shown in FIG. 6.
The logic level of the inverter circuit shown in FIG. 6 can be obtained as follows.
That is, as shown in FIG. 6, suppose conductance constants of the P-type MOSFET and N-type MOSFET are βP and βN, threshold voltages are VTP and VTN, respectively, a supply voltage is VDD, a reference ground potential is 0 and a logic level is VGL. At this time, since the driving capacity of the P-type MOSFET and N-type MOSFET are comparable in the logic level, the following Expression (1) holds.½·βP(VDD−VGL−VTP)2=½·βN(VGL−VTN)2  (1)
By solving this Expression (1), the logic level VGL is expressed by the following Expression (2).VGL={(VDD−VTP+(βN/βP)1/2·VTN}/{1+(βN/βP)1/2}  (2)
Therefore, if various forms of P-type MOSFET and N-type MOSFET are adopted and the conductance constant ratio (βN/βP) is changed from 0 to infinity, the logic level is changed within the range of the following Expression (3).VTN<VGL<VDD−VTP  (3)
At this time, a higher logic level VIH applies when (βN/βP) is 0 and is expressed by the following Expression (4).VIH=VDD−VTP  (4)
On the other hand, a lower logic level VIL applies when (βN/βP) is infinity and is expressed by the following Expression (5).VIL=VTN  (5)
Therefore, a hysteresis width VWHL is expressed by the following Expression (6).VWHL=VDD−VTP−VTN  (6)
However, it is actually impossible to set the conductance constant ratio (βN/βP) to 0 or infinity, and therefore the hysteresis width is actually much smaller than this value.
Therefore, when the supply voltage VDD is a low voltage, for example, approximately 1.5 V, since VTP or VTN is approximately 0.5 V to 0.7 V, the hysteresis width becomes very small and cannot accomplish the original objective.
FIG. 5 shows this situation. In FIG. 5, when an input voltage VIN is 0≦VIN≦VTN, the N-type MOSFET does not operate, and when VDD≦VTP≦VIN−VDD, the P-type MOSFET does not operate, and therefore the logic level of the inverter circuit is limited to a range of VTN<VIN<VDD−VTP.
Since, the threshold voltages VTP, VTN do not fluctuate during operation, when the supply voltage VDD decreases, the range (VDD−VTP−VTN) in which the logic level is available becomes narrower and the hysteresis width becomes very small as the supply voltage decreases.
Therefore, as the conventional circuits shown in FIG. 7, FIG. 8 and FIG. 9, the hysteresis input circuit whose equivalent circuit can be reduced to an inverter circuit has a problem that it is not possible to take a sufficient hysteresis width at a low voltage.
Furthermore, during a low-voltage operation, too, if an attempt is made to set a conductance constant ratio (βN/βP) to secure the hysteresis width as much as possible, it is necessary to change the forms of P-type MOSFETs or N-type MOSFETs to an unnatural extent, resulting in problems of occupying a large chip area, reducing driving capacity or deteriorating responsivity.
Furthermore, in the fourth conventional circuit shown in FIG. 10, since an input terminal 920 is not connected to the gate electrodes of the P-type MOSFET 915 and N-type MOSFET 916, the circuit does not become the equivalent circuit of the inverter circuit shown in FIG. 6 and there are no restrictions on the logic level in FIG. 6.
However, under a design condition under which the hysteresis width should be secured, the first logic level is in effect determined by the N-type MOSFET 912 and P-type MOSFET 915, which results in the following problem.
In FIG. 10, suppose the conductance constants of the P-type MOSFET 915 and N-type MOSFET 912 are βP, βN and threshold voltages are VTP, VTN, respectively. Furthermore, suppose the power supply voltage is VDD, the reference ground potential is 0 and the logic level is VGL. At this time, the following Expression (7) holds approximately.VIL≈(VDD−VTP)−(βN/βP)1/2·(VDD−VTN)  (7)
Here, if the value of (βP/βN) is changed from 0 to infinity, the logic level VIL is expressed by the following Expression (8).−∞≦VIL≦VDD−VTP  (8)
Therefore, the logic level VIL can be set up to a range exceeding the power supply potential. Furthermore, at this time, if a setting is made as Expression (9), the logic level VIL in Expression (7) is expressed by Expression (10).(βN/βP)1/2=(VDD−VTP)/(VDD−VTN)  (9)VIL≈0  (10)
Therefore, the lower limit extends more in this system as opposed to the aforementioned inverter circuit in which the lower limit of the logic level VIL only reaches VTN.
However, at this time, as the condition for setting the second logic level VIL, the setting of the ratio of (βN/βP)1/2 which is the left side to (VDD−VTP)/(VDD−VTN) which is the right side of Expression (9) is a key factor.
However, such a setting is a setting between the P-type MOSFET and N-type MOSFET which differ in nature, and therefore it is rather hard to extend the hysteresis to the very limit when a variation in manufacturing is also taken into consideration.
Furthermore, as is also understandable from Expression (8), even if the logic level VIL is forcibly set low and the logic level VIL falls below potential 0 due to a variation in volume production, there is a problem that even if the potential of an input signal of the input terminal 920 is changed within a range of the supply voltage, a latched state may continue and it may be impossible to recover the operation.
Also when the first logic level VIH is set, a forcible setting to secure the hysteresis width causes the logic level VIH to exceed the supply voltage VDD, causes a latched state to continue, making it impossible to recover the operation.
Therefore, it is an object of the present invention to solve the above described problems and provide a hysteresis input circuit having a relatively large hysteresis width during a low-voltage operation.
It is another object of the present invention to provide a hysteresis input circuit which can realize an input circuit having a relatively large hysteresis width with a reasonable chip area.
It is a further object of the present invention to provide a hysteresis input circuit capable of setting the first logic level and second logic level determining a hysteresis characteristic so that a β ratio among MOSFETs of the same type is set, making a setting to the very limit, securing a large hysteresis width and preventing any situation in which operation is not possible due to manufacturing variations.